Multi-layer PCBs are used in a variety of electrical, electronic and optoelectronic applications for mounting and electrically interconnecting electrical, electronic and/or optoelectronic components. A typical multi-layer PCB comprises layers of organic dielectric substrate material, typically referred to as prepreg, having layers of metal embedded therein that are often patterned to provide electrical signal routing. The metal layers are often interconnected by electrically-conductive vias to allow the electrical signals to be routed vertically through multiple layers of the PCB.
A typical multi-layer PCB manufacturing process is a build-up process in which the layers are built one layer at a time. The build-up process typically comprises using dry dielectric film masking steps to selectively mask regions of a metal seed layer disposed on a starting structure, electroplating onto the unmasked regions of the metal seed layer to form a patterned metal layer, removing the dry dielectric film layer and the metal seed layer below it, laminating a layer of dielectric prepreg material on top of the patterned metal layer, drilling one or more via holes through the laminated dielectric prepreg, cleaning the via holes, forming a metal seed layer on the walls of the via holes, and electroplating metal onto the via holes and onto the non-masked areas of the seed layer to simultaneously fill the via holes with metal and form the patterned metal layer. The process is then repeated to form each additional PCB layer.
On one or both of the outer PCB layers, electrical contacts are formed by electroplating a layer of metal, typically copper, onto the metal seed layer. After the layer of copper has been plated onto the metal seed layer, a finishing layer of metal, which is often a layer of gold (Au) or Nickel-Gold (NiAu), is plated onto the top surfaces of the copper electrical contacts. The exposed portions of the metal seed layer are then etched away. During the process of etching away the metal seed layer, the side walls of the copper electrical contacts also experience etching, which can result in severe overhangs of the Au or NiAu. These overhangs can lead to electrical shorts, cosmetic defects, stringers, and foreign material defects.
FIGS. 1A-1G illustrate cross-sectional views of a multi-layer PCB during the aforementioned known fabrication process that results in overhangs. With reference to FIG. 1A, a PCB having a plurality of inner layers 2 has first and second metal seed layers 3a and 3b, respectively, disposed on opposite sides thereof. Each of the inner layers 2 typically is made up of a dielectric material layer (not shown) and a layer of metal that may be patterned or unpatterned. The dielectric material layer is typically made of “prepreg” that is laminated on top of the metal layer. In the PCB industry, the term “prepreg” denotes a reinforcing fabric made of woven composite fibers that is impregnated with a resin system (e.g., epoxy) that bonds the composite fibers together.
With reference to FIG. 1B, first and second dry dielectric film layers are deposited on top of the metal seed layers 3a and 3b, respectively, and patterned through selective exposure and development steps (photolithography) to form first and second dielectric masks 4a and 4b, respectively, on the first and second metal seed layers 3a and 3b, respectively. With reference to FIG. 1C, first and second layers of copper 5a and 5b, respectively, are then electroplated onto the unmasked areas of the metal seed layers 3a and 3b, respectively. With reference to FIG. 1D, third and fourth dry dielectric film layers are deposited on top of the first and second copper layers 5a and 5b, respectively, and patterned through selective exposure and development steps to form third and fourth dielectric masks 7a and 7b, respectively, on top of the first and second copper layers 5a and 5b, respectively. The copper layers 5a and 5b are the electrical contacts of the PCB.
With reference to FIG. 1E, after the third and fourth dielectric masks 7a and 7b, respectively, have been formed, a thin layer (a few micrometers) of finishing metal (e.g., Au or NiAu) is electroplated onto the unmasked areas of the copper layers 5a and 5b, respectively. With reference to FIG. 1F, the dielectric film layers 4a, 4b, 7a and 7b are stripped away. With reference to FIG. 1G, the exposed portions of the metal seed layer 3a and 3b are then etched away.
When the metal seed layers 3a, 3b are etched away, the etchant also etches away some of the copper layers 5a and 5b, including portions of the side walls of the copper layers 5a and 5b that form the electrical contacts. This can result in the aforementioned Au or NiAu overhangs 9 shown in FIG. 1G, which can lead to the aforementioned problems. In addition, because solder masks are not compatible with the electroplating processes described above, an oxide that serves a function similar to that of a solder mask is applied to the PCB. The oxide further etches the copper layers 5a and 5b, which can further increase the overhang lengths, exacerbating the aforementioned problems.
Accordingly, a need exists for a way to prevent the overhangs, or at least reduce their lengths, in order to prevent the aforementioned problems associated with overhangs.